I saw an article saying that all T-cycles which are in the original msx-documentation should be increased by 1.....

so when an
AND A
instruction uses 4 cycles, it actually uses 5 ?????

Damn right you are. Except for turboR, that is. The turboR only has waitstates when accessing an external slot, internal ROM or internal DRAM.

There are instructions that add 2 cycles.

In http://map.tni.nl/resources/z80instr.php you should see almost everything that you need about timing.

I wonder how we can disable this waitstate in the msx... and will it still work without

I'd like to have the waitstate for external slots @ turboR removed... My memory mapper is damn slow this way

Turbo R has the same waitstates in z80 mode. In R800 mode there are also added waitstates for memory refresh, but not as many and the amount depends on the amount of memory. A 512k tR is therefore a bit slower than a 256k version. Fun thing is, that the 1MB has actually the same speed as a 256k tR. Probably because the extension implements much of the mapper logic itself.