I did some tests with a loop that constantly wrote to VRAM using the VDP, and it seemed to work fine, have I misunderstood something?
Did you do this on a real MSX? IF so then you have a very strange MSX
If you write to vram at same time the VDP is building the screen you'll get distortions.
ei
halt
di
This works fine if only the VDP generates interrupts. But if you plug in additional hardware which also generates INTS you wont be able to tell if it comes from the VDP on not.
Then I do have some issues with setting gfx modes. The BIOS way works fine to set Screen 1 (32x24 text mode). However when I set Screen 0, I get
40x24 as expected in emulator, but on my real MSX (NMS8245) instead I get some kind of MSX2 mode with 80 characters wide screen.
The 80x24 is set by setting:
ld a,80
ld (&hf3ae),a ;width 80
when calling the bios for textmode,it will look at that address to determine the width.
I also tried setting modes with the VDP directly, using the code hitchhiker posted, but then I only get garbage on screen no matter what mode I try. Strange...
If setting the mode yourself through the vdp-regs then you'll have to wipe clean the vram yourself. If you do it through the bios,the bios wipes it for you.
when working on a msx2 @3.5Mhz (V9938 VDP) you can output data to vdp at full z80 speed, even outside VBLANK, no problem at all.
when working on a msx1, (TMS VDP), the maximum speed you can achieve depends if you are in vblank or not.
outside vblank, every byte write or read should wait almost 26 z80 T-States (including the instruction that write data to VDP port 98h)
in vblank, no limit or delay.
Ahh! OK, that clears things up and makes more sense. The code I was testing with was my plasma code that actually does a bit of calculation for each output:
ld a,ix+XP add a,b out (c),a
Haven't counted how many T-states that is, but if I recall correctly the ix instructions takes quite a few.
And then I was testing it on my MSX2, but it would be nice to be able to write code that is MSX1 compatible.
Am I right in assuming that no emulator emulates this correctly, so the only way to know for sure that you don't stress the VDP too much is to test on a real computer?
For waiting for interrupts the tecnique below is OK, however i do not know why you disable ints
ei
halt
My thought was that I didn't want an interrupt going off when I was doing my VDP stuff, since I read that it could mess things up, but as long as I finish my code before next VBL, I guess it shouldn't be a problem having interrupts on all the time.
to get a good setup of the screen mode, you need also to intialize the VRAM....
The rest of the program was the same as before, so the VRAM has stuff written to it.
Ie. before I had like this:
1) Set Screen 1 using BIOS
2) Do effect
and I instead changed to
1) Set Screen1 using VDP
2) Do effect
And only got garbage.
This works fine if only the VDP generates interrupts. But if you plug in additional hardware which also generates INTS you wont be able to tell if it comes from the VDP on not.
OK, what is the correct procedure for a VBL wait if you want to be compatible with expanded units?
Also, thanks to everyone for helping out. I apologize for bombarding you with all these newbie questions!
when working on a msx1, (TMS VDP), the maximum speed you can achieve depends if you are in vblank or not.
outside vblank, every byte write or read should wait almost 26 z80 T-States (including the instruction that write data to VDP port 98h)
Actually, it's not 26 T-states but 29 T-states (8µs @ 3.579545 MHz)
ei halt di
(Enable interrupts, wait for it, then disable again)
Is that a sensible way to make a VBL wait?
This method should work ok, if you don't have MIDI or some other devices generating ints. How ever EI has effect in one command delay, so I think the code should be:
EI NOP HALT DI
Another thing ... If you like demos, probably you will use the PSG too.
There is the infamous "malware" that apparently was even spread to some MSX cartridges and books when the programmers do not correctly set the bits on the registers. Since the PSG is used to read from the game ports a program should not mess with the I/O part. This is even more important than the Video timing on non (MSX2) MSX-Video processors ... This was/is rumoured to be potentially dangerous to the MSX microcomputer.
Another thing ... If you like demos, probably you will use the PSG too.
There is the infamous "malware" that apparently was even spread to some MSX cartridges and books when the programmers do not correctly set the bits on the registers. Since the PSG is used to read from the game ports a program should not mess with the I/O part. This is even more important than the Video timing on non (MSX2) MSX-Video processors ... This was/is rumoured to be potentially dangerous to the MSX microcomputer.
The term 'malware' is a bit exaggerated. 'Malware' refers to software that intentionally damages the system, and as far as I know, no MSX software was written with the intention to damage the computer it runs on.
The two upper bits of register 7 of the PSG control the function of its two I/O ports, of which the values are in regs 14 and 15. Port A (reg 14) must be configured as input, port B (reg 15) as output, meaning that register 7 must always contain %10xx xxxx. On some MSX1 models the lines to the joystick ports are not buffered, which means that an incorrect set up of register 7 could, indeed, potentially blow up the PSG.
ei halt di
(Enable interrupts, wait for it, then disable again)
Is that a sensible way to make a VBL wait?
This method should work ok, if you don't have MIDI or some other devices generating ints. How ever EI has effect in one command delay, so I think the code should be:
EI NOP HALT DI
Almost every MSX device creates interrupts : floppy disk drive, FM Pac, Music Module, ...
Therefore, you should not use halt to wait for a VBLANK interrupt.
Another thing ... If you like demos, probably you will use the PSG too.
There is the infamous "malware" that apparently was even spread to some MSX cartridges and books when the programmers do not correctly set the bits on the registers. Since the PSG is used to read from the game ports a program should not mess with the I/O part. This is even more important than the Video timing on non (MSX2) MSX-Video processors ... This was/is rumoured to be potentially dangerous to the MSX microcomputer.
The term 'malware' is a bit exaggerated. 'Malware' refers to software that intentionally damages the system, and as far as I know, no MSX software was written with the intention to damage the computer it runs on.
The two upper bits of register 7 of the PSG control the function of its two I/O ports, of which the values are in regs 14 and 15. Port A (reg 14) must be configured as input, port B (reg 15) as output, meaning that register 7 must always contain %10xx xxxx. On some MSX1 models the lines to the joystick ports are not buffered, which means that an incorrect set up of register 7 could, indeed, potentially blow up the PSG.
Actually, I believe that the newspaper reported this as some sort of "Virus" ... Sure that since it was already reported, most of the contemporaneous programs are corrected before getting a cartridge release.
I do not know if it was 'intentional' or not ...
when working on a msx1, (TMS VDP), the maximum speed you can achieve depends if you are in vblank or not.
outside vblank, every byte write or read should wait almost 26 z80 T-States (including the instruction that write data to VDP port 98h)
Actually, it's not 26 T-states but 29 T-states (8µs @ 3.579545 MHz)
No, i tested on the unfamous Sony HB-10P with the vdp clone. (write of 6144 bytes continuosly) This model is knew to be the slowest in VRAM Access.. With 26T-States there is no corruption even with ALL SPRITES ON (the worst case)
(i have 32 sprites of 16x16 pixels on screen arranged on a 4x8 matrix)
So the effective time is about 7.2 us
No, i tested on the unfamous Sony HB-10P with the vdp clone. (write of 6144 bytes continuosly) This model is knew to be the slowest in VRAM Access.. With 26T-States there is no corruption even with ALL SPRITES ON (the worst case)
(i have 32 sprites of 16x16 pixels on screen arranged on a 4x8 matrix)
So the effective time is about 7.2 us
Mmm. I'm not sure that disabling/enabling the sprites would make a difference in VRAM access speed when considering MSX1 machines. Has anyone tested this? I know that it is true for V99x8 enabled computers, but I doubt that it would make a difference in a TMS99xx or compatible VDP.