Hi!
In my work with a proper memory mapper for SVI738, understand that the SLT logic is not correct, and does modes for adding 256-4MB dram that Henrik Gilvad introduce do not work as expected to the MSX2/MSX2+ standard.
Even that we can do a conversion with VRAM 128KB and BIOS for MSX2/MSX2+ with replace of the VDP works we still have the issue with the mapper. Even if we successfully have a mapper working we will have that RAM in SLT2 or SLT1, which is not as the MSX2/+ standard apply, we would like to have it on SLT3-2 or SLT3-3.
So in this work, I decide to go for the ULAs and replace does with CPLD, specially the ULA9RA041 but also the ULA5RA087
do get replacement if does are broken 
, I have study the MSX Data Pack, Expert 2/3 schematics, also some PHILIPS manual, Yamaha and Sony to try to reverse engineer does ULA, and correct the ULA9RA041 logic, to get a correct mapping of SLT3-x and also the FFFF signal.
I think I have made a embryo, but please advice or comment the schematics, also a VHDL project will start, if you are good a VHDL and want help .. please contact me
The new ULA replacement for ULA9RA041 have added logic and will need additional Adrees Ports A2-A5 and A7-A13
and the pin 40 is not used anymore, also the (parts of IC) IC42 and IC29 are not in used, new signal will be connect direct to pin 1 on IC63 also pin46 will be connected direct to /SLT3 signal as input
Idea is to use socket that connect to CPLD (MAX 7000S) for replacement as PIGBACK PCB
