I assume there's a connection with the vram fetch timings. Notice how the data for the (bitmap) pixels is fetched in 32 blocks of 8 pixels.
Yes, this seems very likely and logical.
It's hard to correctly emulate this behavior without _much_ more information on the exact inner workings of the V99x8
Indeed this seems a bit hard as you can not even say that this register works like this and that register like something else. The screen modes seem to affect things and if you take ie. register 25 it seems that bit 0 (SP2) has this 8-pixel fixed place to affect while ie. bit 3 (YJK) and 4 (YAE) seem to affect immediately without any delays:
SP2:
YAE:
I suggest you get on to that, my dear Dolphin101546015!
My dear Manuel, so you consider this problem only mine, and I will solve it alone.
It's pity, because it just means that I need to stop using OpenMSX for development unless I have other solutions.
Thanx. 
