@lintweaker
Hi,
are you full aware the cycle timing of Z80 in MCLZ8 is not respecting the T-state count in mode 0 (that is, emulating all the genuine T-states of a Z80)? For instance, the ED instruction table for cycles is wrong: it doesn't remove the 4 T-states in the table due to the execution of prefix ED. So for instance, IM 1 (ED56) will take 12 cycles (4,4+4) on MCLZ8 instead of 8 cycles (4,4) on genuine Z80. Of course, if you're just using mode 3, that won't be an issue.
Not only that, instructions involving a jump or a call add hardcore cycles doubling the extra ones in their opcode table. So a CALL nnnn will take 22(4,3,4+6,3,3) on MCLZ8 instead of 17(4,3,4,3,3) on genuine Z80.
Do you have a correction for the HALT behavior? You were right, HALT shouldn't do a "--register_pc;". As a true genuine Z80, it should set a HALT flag and when Z80 is fetching opcode, it must check that flag to execute a NOP instead of that opcode and to not increment PC. That way, INT or NMI are just resuming from the next instruction after HALT without needing to adjust PC. And that's how a genuine Z80 does.
Regards.
