Updated manual location is here.
Please bookmark it, and check again to confirm that I did modifications correctly.
albs_br wrote:
... on page 60, the table with addresses is with the final 2 addresses wrong: it is 27134 and 27135, should be 54270 and 54271 ...
Fixed.
ducasp wrote:
There is an error also on page 56, it says that gor G6 the R#2 seeting of A16 is bit 7 = 0, bit 6 = A16 and bits 5 to 0 = 1, where the Yamaha documentation (and the real thing behavior) is bit 7 and bit 6 = 0, bit 5 = A16 and bits 4 to 0 = 1
Fixed.
ducasp wrote:
It ends up that page 58 has an error in its title, it is saying example of VRAM allocation for GRAPHICS 4 mode, it should be GRAPHICS 6 mode
Fixed.
Grauw wrote:
The part I struck through in the quote above should be removed. The dots with 0 in the sprite pattern are always transparent and do not have a color code. The value of TP does not affect them. The color of the dots with 1 in the pattern is specified by the sprite attributes. When the sprite color attribute is 0, the TP flag determines whether these dots are transparent or opaque.
Fixed.
Dolphin101546015 wrote:
When I write PAINT, I found wrong function codes for SEARCH or POINT (Dont remember actualy, coz not using manual anymore). But I'm ready show my own codes functions list.
Need more information on it. Can not find the location of the wrong function codes. SRCH=0110 and POINT=0100.
In the TEXT2 mode and in bit map modes of GRAPHIC4 to GRAPHIC7 two pages can be alternatively displayed (blinked). Write to this register R#13 in order for blinking to start.
All the VDP Registers pages are now in a sub-category 'VDP Registers', with exception for the 'intro page". I had to copy/paste the content of this intro page (VDP Registers) as Move can't be used to transfer a normal page into a category.
Error [p16]: « VDP can logically address 128K bytes in the address range of 00000h-1FFFFh through 16 address bits A16...A0. »
> It is 17 bits instead of 16.
Clarification [p21]: « In all modes, except GRAPHIC1, GRAPHIC2, MULTICOLOR and TEXT1, if there’s a carry flag from A13 the value in this register is automatically incremented. »
> Specify that the carry comes from the automatic incrementation of the address during sequential accesses. Not obvious imo.
