Where we can find one?
As I read, it have cost under $50, but where you bought it?
Hello Giuseve,
Your outline is absolutely right.
Otherwise, you can use it as a stand-alone machine w/o joysticks and the slot yet. Also, no competition.
I have no intentions to sell this or make any kind of business/money.
The schematics will be published and the layout too. (as all the Novatec projects 
)
You can visit the web site to see, that this card is a "side effect" of a different development.
The BOM is about 30$, the 2 layers PCB is about 15$ at a quantity starting from 30.
For 3 protos, I have payed per card: 45$ components+50$ per PCB card (the tooling cost is high for small batches).
For small series the automatic assembly, testing and packaging has to be included.
Cheers,
DL
Where we can find one?
As I read, it have cost under $50, but where you bought it?
Well, it was designed by me, then, small batch of PCBs was ordered together with the components. Then I've soldered one card. It is operational, but requires further FPGA development. This is what I'm doing now
Hi maxis,
Performance wise, what can we expect? vdp and z80 speed?
Would-be nice if we can get a msx with equal or more speed then Turbo R 
Hi maxis,
Performance wise, what can we expect? vdp and z80 speed?
Would-be nice if we can get a msx with equal or more speed then Turbo R
Well, it depends on the particular implementation of Z80 and VDP. When for the sake of testing synthesized in Spartan6 the high performance multichannel SDRAM controller, the Xilinx ISE static analysis tool with Spartan XC6SLX9 3C target told me that the design can run at 180 MHz. So, if you like, you can download XILINX ISE webpack, take OCM and re-synthesize it with the XC6SLX9 3C target. Take a bigger package in order not to hit the pin count constraints. Then, you can compare the results.
To cut it short, the power distribution system is designed to provide enough amperes with nominal ripple to power the device at 99.9% utilization at the maximum speed. I haven't done the burn-in test yet, but another test design using internal PLLs to synthesize the pixel clock beyond 100 MHz for SXGA (1280x1024) to run HDMI is working. Spartan6 is very capable device (faster than VirtexII for the same benchmarking tasks).
Currently I'm attempting to build the VDP with the tightly coupled multichannel SDRAM memory controller. The datapath is 16bits (same as the SDRAM data bus). Also I have a 16bit Z80 somewhat compatible processor (but not cycle accurate, no I & R registers, IM1 mode only, pipelined, 1 cycle/opcode execution). If this approach is taken, then the execution speed can be roughly 30 Z80 MIPS@ 30MHz comparing to 1 MIPS@4MHz of the original Z80 (0.7 MIPS on MSX). Then, the acceleration can be at least x30 times comparing to the original 3.57MHz machine. But then the question is - how accurate would be the emulation and whether this is needed.
